Product Summary
The SN74LVC1G125DBVR is a single bus buffer gate with 3-state output. It is is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G125DBVR is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74LVC1G125DBVR when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Parametrics
SN74LVC1G125DBVR absolute maximum ratings: (1)VCC Supply voltage range: –0.5 to 6.5 V; (2)VI Input voltage range(2): –0.5 to 6.5 V; (3)VO Voltage range applied to any output in the high-impedance or power-off state(2): –0.5 to 6.5 V; (4)VO Voltage range applied to any output in the high or low state(2) (3): –0.5 to VCC + 0.5 V; (5)IIK Input clamp current VI<0: –50 mA; (6)IOK Output clamp current VO<0: –50 mA; (7)IO Continuous output current: ±50 mA; (8)Continuous current through VCC or GND: ±100 mA; (9)θJA Package thermal impedance(4) DRL package: 142℃/W; (10)DRY package: 234℃/W; (11)YZP package: 132℃/W; (12)DBV package: 206℃/W; (13)DCK package: 252℃/W; (14)Tstg Storage temperature range: –65 to 150℃.
Features
SN74LVC1G125DBVR features: (1)Available in the Texas Instruments NanoStar and NanoFree Packages; (2)Supports 5-V VCC Operation; (3)Inputs Accept Voltages to 5.5 V; (4)Max tpd of 3.7 ns at 3.3 V; (5)Low Power Consumption, 10mA Max ICC; (6)±24mA Output Drive at 3.3 V; (7)Ioff Supports Partial-Power-Down Mode Operation; (8)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II; (9)ESD Protection Exceeds JESD 22.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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SN74LVC1G125DBVR |
Texas Instruments |
Buffers & Line Drivers SINGLE BUS BUFFER GATE |
Data Sheet |
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